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Signal DescriptionsTable 2-5 describes the signals. With the exception of the JTAG pins, the GPIO function is the default atreset, unless otherwise mentioned. The peripheral signals that are listed under them are alternatefunctions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputsare not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabledor disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pinsare not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do nothave an internal pullup.NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38pins could glitch during power up. If this is unacceptable in an application, 1.8 V could be suppliedexternally. There is no power-sequencing requirement when using an external 1.8-V supply. However, ifthe 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.9-Vtransistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during powerup. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins, ensuring thatthe VDD pins have reached 0.7 V before the VDDIO pins reach 0.7