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Memory Bus (Harvard Bus Architecture)As with many MCU-type devices, multiple busses are used to move data between the memories andperipherals and the CPU. The memory bus architecture contains a program read bus, data read bus, anddata write bus. The program read bus consists of 22 address lines and 32 data lines. The data read andwrite busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enablesingle cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables theC28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals andmemories attached to the memory bus prioritize memory accesses. Generally, the priority of memory busaccesses can be summarized as follows:Highest:Data Writes(Simultaneous data and program writes cannot occur on thememory bus.)Program Writes(Simultaneous data and program writes cannot occur on thememory bus.)Data ReadsProgram Reads(Simultaneous program reads and fetches cannot occur on thememory bus.)Lowest:Fetches(Simultaneous program reads and fetches cannot occur on thememory bus